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Fachzeitschrift für Hochfrequenz- und Mikrowellentechnik

RF & Wireless Figure 5:

RF & Wireless Figure 5: Double click on the MTRACE and three black dots (handles) appear on the MTRACE represents Port 1 of the element. Electrically, it does not matter if the MTRACE is connected with Port 1 on the other side. However, Port 1 is where the routing of the MTRACE in the layout environment is begun. In the layout editor, Port 1 is indicated by a blue triangle on one of the ends of the MTRACE layout. The first step in adding bends to the line is to double click on the MTRACE. Three black dots (handles) appear on the MTRACE, as shown in Figure 5. Move the mouse cursor to Port 1 (blue triangle) of the MTRACE. The mouse cursor will become Figure 6: Bends in the MTRACE cause a slight change to the S-parameter a double-arrow sign when it is at Port 1. Since the length of the MTRACE is calculated, it is necessary to maintain the line length when the bends are added. In this situation, hold down the SHIFT key throughout the routing process. While the SHIFT key is held down, double click on Port 1. Begin routing the line and bending it. Be sure the SHIFT key is held down, otherwise the line length will be changed after the routing process is completed. Double click when finished routing the MTRACE. Note that in this case, three bends have been added to the top MTRACE. The bottom MTRACE has the same number of bends (and same angles) because the DB and RB have been set to track the top MTRACE (in other words, MTRACE2.X1). To flip the bottom MTRACE to the correct direction, select it, right click, and select FLIP. In the schematic, note that the length of the MTRACE has been maintained. Double click on the MTRACE element and notice that the DB and RB parameters now indicate the number of bends added and the associated angles. Simulate the circuit again. It can now be seen in Figure 6 that there is a slight change of S-parameters due to the added bend models in the MTRACE. Align the input 50-ohm line, the MTEE$ junction, and the two MTRACES and snap them together. Then connect the MTRACES to the resistor. The entire layout is a loop. In order to connect the MTRACES exactly with the resistor’s solder pads, make one of the solder pads stretchable. This is done by right clicking on the solder Figure 7: Make one of the solder pads stretchable by right clicking on it and selecting “Shape Properties” Figure 8: EXTRACT block. 72 hf-praxis 6/2017

RF & Wireless Figure 9: The red lines are simulated using ACE, taking coupling effects into account Figure 10: Power divider dimensions Figure 11: Compacted power divider pad (Figure 7), selecting SHAPE PROPERTIES and then enabling STRETCH TO FIT. Select all (CTRL-A) and snap all of the elements together. One of the solder pads stretches itself so that the connection is made. This will introduce a very high inductive parasitic that is not desired. To fix this, go to OPTIONS/ LAYOUT OPTIONS and set to AUTO SNAP mode. The top MTRACE can now be adjusted to minimize the length of the solder pad. Double click on the MTRACE and move the handles (black dots) as appropriate. The layout of the power divider is now complete. Re-simulate the circuit and see the effects of the bends and the slightly modified solder pad length. Accounting for coupling The next step is to determine how to handle couplings between sections in MTRACE. MTRACES are basically a series of MBENDs and MLINs. The mutual coupling between MLIN sections are not included in the simulation. To account for the mutual coupling, there are two options, the first of which is EM simulation. EM simulators should be used as a verification tool, so in this case, where moving the lines around and quickly analyzing the coupling effects is desired, EM simulation is not the best choice. A design tool is needed that can quickly extract the coupling effects and simulate within seconds. Automated circuit extraction The second option is to use ACE automated circuit extraction technology. ACE is a design tool that very quickly extracts highly accurate high-frequency models of the layout, including coupling effects. The tool can be used to make changes to the layout and evaluate the resulting S-parameters while considering coupling issues without having to do a full EM simulation. In this way, RF circuits can be compacted very quickly. EM simulation is only invoked at the end of the design process in order to verify the design. In this example, ACE is employed to evaluate the coupling between the microstrip sections. Set ACE by first setting up the STACKUP, then selecting which lines are needed to extract the coupling and, finally, inserting the EXTRACT block. To evaluate the coupling between the microstrip lines, select the two MTRACES and 50-ohm output lines and name them “Lines.” The EXTRACT block is then added referencing the name Lines and ACE is invoked (Figure 8). Note that once ACE is set up, it is very easy to simulate coupling between microstrip lines. The lines in Figure 9 (red) are being extracted to perform an ACE simulation, so the coupling effects can be considered. In this way, the designer can adjust the layout to the desired size and then an EM simulation can be done on the layout as a final verification. Step 4: Circuit Compaction Now the physical design of the power divider is complete, the next objective is to further miniaturize the layout. The power divider that was laid out has the dimensions (DRAW/DIMEN- SION LINES) shown in Figure 10 and now needs to be evaluated to see if it can be made smaller. By re-routing the MTRACE, an exercise now left to the reader, a smaller layout (Figure 11) can be achieved. Once again ACE can be deployed to extract the coupling effects that will be taken into account during the layout adjustments and circuit simulation. Line lengths of the MTRACEs can be tuned along with ACE, and, eventually, AXIEM 3D planar EM simulator is used for final EM verification (Figure 12). Conclusion This application example has described the steps for designing a Wilkinson power divider, including design using ideal transmission lines, microstrip implementation, physical design, and circuit compaction. The entire design was done using NI AWR Design Environment, specifically Microwave Office for the design from schematic entry to physical PCB implementation, ACE for evaluating the coupling between the microstrip sections, and AXIEM for final EM verification. National Instruments ni.com/awr Figure 12: ACE and AXIEM EM simulation results (light and dark pink lines) vs ideal circuit hf-praxis 6/2017 73

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