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vor 7 Jahren

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Fachzeitschrift für Hochfrequenz- und Mikrowellentechnik

Aus Forschung und

Aus Forschung und Technik Vertikal gestapelte „Gate-all-around-Si“ Nanowire-CMOS- Transistoren kommen in Reichweite Beim International Electron Devices Meeting 2016 (IEDM) - im Dezember in San Francisco - berichtete imec erstmals über die CMOS-Integration von vertikal gestapelten „Gate-all-around (GAA)“ Silizium Nanowire MOSFETs. 1/8_Inserat_4c_Layout 1 04.12.14 IMEC 11:0 www.imec.be Komponenten und Systeme für HF- und Mikrowellentechnik Absorbierende Materialien Übertragungsstrecken Anschlüsse und Leitungen Antennen/Antennensysteme EMV-Messzubehör Frequenzquellen Gehäuse und Frästeile Komponenten Schalter und Verteilsysteme Verstärker/Verstärkersysteme Wir liefern Lösungen ... www.telemeter.info (a) Top view SEM image after PWFM etch form the n-FETs, and (b) – (d) cross-sectional TEM images of p- and n-FETs at the end of process (L G = 30 nm) Key in the integration scheme is a dual-work-function metal gate enabling matched threshold voltages for the n- and p-type devices. Also, the impact of the new architecture on intrinsic ESD performance was studied, and an ESD protection diode is proposed. These breakthrough results advance the development of GAA nanowire MOSFETs, which promise to succeed Fin- FETs in future technology nodes. GAA nanowire transistors are promising candidates to succeed FinFETs in 7 nm and beyond technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In a horizontal configuration, they are a natural extension of today’s mainstream FinFET technology. In this configuration, the drive current per footprint can be maximized by vertically stacking multiple horizontal nanowires. Earlier this year, imec scientists demonstrated GAA FETs based on vertically stacked 8 nm diameter Si nanowires. These devices showed excellent electrostatic control, but were fabricated for n- and p-FETs separately. Imec now reports on the CMOS integration of vertically stacked GAA Si nanowire MOSFETs, with matched threshold voltages for n- and p-type devices. [Lit.: “Vertically stacked gateall-around Si nanowire CMOS transistors with dual work function metal gates”, H. Mertens et al., IEDM 2016]. Key in the integration scheme is the implementation of dualwork-function metal gates to set the threshold voltages of the n- and p-FETs independently. In this process step, p-type work function metal (PWFM) is deposited in the gate trenches of all devices, followed by selectively etching the PWFM down to the HfO2 from the n-FETs and subsequent deposition of the n-type work function metal. The observation of matched threshold voltages (VT, SAT = 0.35 V) for nMOS and pMOS devices validates the dual-work-function metal integration scheme. The impact of this new device architecture on the intrinsic ESD performance was investigated as well. [Lit.: “ESD diodes in a bulk Si gate-all-around vertically stacked horizontal nanowire technology”, S.-H. Chen et al., IEDM 2016] Two different ESD protection diodes have been proposed, i.e. a gate-structure defined diode (gated diode) and a shallowtrench isolation defined diode (STI diode). The STI diode was the better ESD protection device, showing an excellent ratio of failure current (It2) over parasitic capacitance (C). Measurements and TCAD simulations also prove that the ESD performance in GAA nanowire based diodes is maintained in comparison to bulk FinFET diodes. “GAA Nanowire Transistors enable ultimate CMOS Device Scaling, with low degreee of added complexity compared to alternativee sclaing scenarios,” stated Dan Macuta, Director Logic Device and Integration at IMEC. The proposed integration scheme for Si GAA CMOS Technology and the results on ESO protection are important achievements towards realizing these 7 nm and beyond technology nodes. Future work will focus, among others, on further optimizing individual process step , for example through the co-optimization of the junction and nanowire formation.” Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC. ◄ 32 hf-praxis 3/2017

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